The present invention relates to a PLL (Phase Locked Loop) circuit and a recording and playback apparatus using the same and, particularly, to a PLL circuit suitable for use as a clock recovery circuit of a recording and playback apparatus whose head crosses tracks during search and a recording and playback apparatus using the same as a clock recovery circuit.
A signal processing method referred to as PRML (Partial Response Maximum Likelihood) for a recording and playback apparatus, such as a tape streamer, a hard disk apparatus, and an optical disk apparatus, has recently been drawing attention. The PRML signal processing method is a technique that makes it possible to increase recording density by a factor of 1.2 to 1.5 by a signal processing without greatly changing an existing recording and playback system.
The description in the following will be made by taking a tape recording and playback apparatus employing a helical scanning method as an example of the recording and playback apparatus. When the tape recording and playback apparatus searches on an azimuth-recorded magnetic tape, as shown in FIG. 18, a trajectory of the head becomes inclined more than recording tracks do. A waveform (envelope) of a signal reproduced during the search is shaped like so-called abacus beads, which are rhombuses arranged in a row, as shown in FIG. 19.
When a search is made at a centuple speed, for example, the head crosses about 100 tracks. In the case of azimuth recording, a head cannot read a signal on an adjoining track, and therefore the waveform of the reproduced signal reaches its peak once every two tracks. As a matter of course, only a noise component is produced at a valley between two peaks. Also, even when a mechanical compensation is provided during the search, the frequency of data reading is usually changed slightly (about +/xe2x88x922%).
FIG. 20 is a configuration block diagram of a clock recovery section used in a common PRML signal processing method. The clock recovery section has a configuration of a PLL circuit, comprising a phase comparator 101, a loop filter 102, and a VCO (voltage-controlled oscillator) 103. The phase comparator 101 comprises a sampling circuit 111, an arithmetic circuit 112, and a tentative determination device 113.
In ternary (1, 0, xe2x88x921) data detection, an amplitude value of the data is converted into phase error information, as shown in FIG. 21. FIG. 21 shows a case where a clock is delayed. In FIG. 21, ∘ denotes true data timing, and xe2x80xa2 denotes actual data timing.
In order to convert the amplitude value of the data into the phase error information, it is necessary to know whether the data detected is 1, 0, or xe2x88x921. Therefore, the phase comparator 101 generally uses the tentative determination device 113. The tentative determination device 113 provides a result of tentative determination of 1, 0, or xe2x88x921 by comparing the data with two threshold levels TH and TL.
In the case of FIG. 21, the result of tentative determination is changed in a sequence of 0, 1, 0, and xe2x88x921 at times a to d. Therefore, data at the time a is reversed and data at the time c can be used as it is as phase error information. When letting St be a sample value (t is a clock #), Dt be a tentative determination value, and Pt be a phase output, the arithmetic equation is expressed as follows:
Pt=Stif Dt=0 and Dt+1=1
Pt=Stif Dt=0 and Dt+1=xe2x88x921
There are various partial response methods, and there are various data processing methods other than that shown in FIG. 21, in which phase error information is outputted only when the tentative determination value is zero. The arithmetic method of the arithmetic circuit 112 differs accordingly, but the fundamental concept is the same. Although data obtained after Viterbi decoding may be used instead of employing the tentative determination device 113, this enlarges the loop and results in higher susceptibility to delay.
PLL behavior under such conditions will be analyzed. In this case, it is supposed that sampling timing of the tentative determination device 113 and timing of the data are different from each other. Such difference in timing seems unnatural; however, in the case of an actual circuit, even at for example 100 Mbits/sec, a value very commonly observed with a current technique, the bit width is 10 nsec and 1% of that is 100 ps.
A delay on the order of this value can occur as a clock skew between latches of a flash A/D converter, for example. When the delay is to be handled in an analog fashion, a tentative determination comparator and a sampling comparator are often provided separately. Thus, a sampling timing difference (delay) of 1 or 2% of a 1-bit width greatly affects the PLL behavior.
The results of analysis are summarized as follows.
(1) When a waveform obtained during a search is made substantially flat by being passed through an AGC (Automatic Gain Control) circuit, the PLL is disturbed due to the effects of noise occurring during track crossing. The noise effects depend heavily on the above-mentioned error in timing between the data and the tentative determination device 113, and the tolerance for the error is about +/xe2x88x922%.
(2) When there is a difference between an oscillating frequency of the VCO 103 and a data rate, the tolerance is further reduced to about half that of (1). In addition, a range of tolerable delay differs according to whether the frequency is high or low.
Thus, unless the delay between the data sample and the tentative determination device 113 is precisely controlled to be infinitely close to zero, a stable search cannot be made, and thus substantially no design margin is allowed.
The reason why such a problem arises is as follows. The PLL behavior is disturbed by noise, and when there is a frequency deviation, the PLL behaves to eliminate the difference. In the former case, a smaller loop gain (lower natural frequency xcfx89n) is advantageous, whereas in the latter case, a larger loop gain (higher natural frequency xcfx89n) is advantageous. Thus, it is difficult to make a setting at a point of compromise between these values.
The present invention has been made in view of the above problems, and it is accordingly an object of the present invention to provide a PLL circuit and a recording and playback apparatus using the same that can stabilize the search operation and increase the design margin by preventing the PLL behavior from being disturbed by noise.
A PLL circuit according to the present invention includes: a loop circuit section including a phase comparator, a loop filter, and a voltage controlled oscillator for generating a clock on the basis of an input signal; and control means for determining that the level of the input signal is at or lower than a specified level and then holding PLL operation of the loop circuit section on the basis of the result of the determination. The PLL circuit is used in a recording and playback apparatus as a clock recovery circuit that generates, on the basis of the signal read from a recording medium, a sampling clock for an A/D converter for subjecting the signal to A/D conversion.
When the PLL circuit thus comprised and the recording and playback apparatus using the same as a clock recovery circuit detect that the level of the signal read from a recording medium is at or lower than a certain level during track crossing for a search, the PLL circuit and the recording and playback apparatus hold the PLL operation. Therefore, the PLL behavior is not disturbed by a noise component occurring during track crossing. Thus, it is possible to stabilize the search operation and substantially increase the design margin.
Another PLL circuit according to the present invention includes: a loop circuit section including a phase comparator, a loop filter, and a voltage controlled oscillator for generating a clock on the basis of an input signal, the PLL circuit supplying the clock generated by the loop circuit section to an A/D converter for subjecting the input signal to A/D conversion; first delay means for delaying the generated clock and then supplying the clock to the A/D converter; and second delay means for delaying the generated clock and then supplying the clock to the phase comparator.
It is preferable to provide a relative delay between the clock supplied to the A/D converter through the first delay means and the clock supplied to the phase comparator through the second delay means. The PLL circuit is used in a recording and playback apparatus as a clock recovery circuit that generates, on the basis of the signal read from a recording medium, the sampling clock for the A/D converter for subjecting the signal to A/D conversion.
The PLL circuit thus comprised and the recording and playback apparatus using the same as a clock recovery circuit provide a relative delay between the clock supplied to the phase comparator and the clock supplied to the A/D converter, whereby there are greatly increased chances of the phase comparator determining phase delay, for example. Therefore, the PLL behaves actively to advance the phase when the phase is delayed. As a result, the PLL quickly makes a transition to a phase-locked state. Thus, it is possible to realize a more stable search operation and substantially increase the design margin.